(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for measuring the surface quality or smoothness of a deposited layer of Hemispherical Grain (HSG) polysilicon, by coating the HSG with photoresist (PR) or Spin-On-Glass (SOG), and determining the amount or absorbed PR of SOG.
(2) Description of the Prior Art
Semiconductor manufacturing has, over the last several decades, accomplished significant improvements in device performance driven to a large degree by a continued decrease in device dimensions. This continued decrease in device dimensions has been made possible by continued improvements in the technologies that are used to create semiconductor devices, most notable are photolithography and the developments of increased contrast photoresist materials. The creation of micron and sub-micron devices brings with it the requirement that extremely small device features can be created which, in turn, brings with it the requirement that light-beams or any other source of radiation used for the creation of these features is well controlled. This control extends not only to effects of exposure energy delivery and focusing but also to avoiding reflective light scattering caused by layers underlying the exposed photoresist layers. Reflective materials, underlying the photoresist, can cause degradation in sub-micron device features to occur due to reflective light scattering.
One of the methods used to reduce the scattered light phenomenon is the use of anti-reflective coating (ARC) which is a polymer film that is, for the exposure wavelengths, highly absorbing and non-bleaching. The light absorption by the ARC coating reduces the intensity of the reflected light and, in so doing, allows critical dimensions of device feature size to be accomplished. The ARC coating can typically be applied directly to the surface of a substrate after which the photoresist can be deposited on top of the ARC coating. ARC coating can also be applied to the construction of more complex device features such as, for instance, gate structures for MOSFET devices. The ARC coating can also be combined with the deposition of other materials such as the insertion of a layer of TiN between the photoresist and the underlying gate material. This approach however results in more complex and therefore more expensive processing steps since the layer of TiN must, after the photoresist has been patterned and the gate features have been etched accordingly, be removed. This removal in turn may add to minute product contamination and further process complexity. The application of an ARC coating however partially planarizes the wafer topography thereby reducing light scattering effects. The underlying layer of ARC makes the layer of photoresist more uniform, which helps to reduce variations in line width of device features.
Wafer topography also has a significant impact on reflective light characteristics. A surface topography that has large differences in height between device features aversely affects photoresist imaging further aggravating the reflective light scattering effect during photoresist imaging.
For instance, for the creation of MOSFET devices, the device channel length is of critical importance where the shortest channel length is desired. Field oxides are created adjacent to the gate electrodes for device isolation purposes, these field oxides form relatively thick layers which leads to a rough surface topography which leads to increased light scattering effect which in turn makes the creation of critical small channel lengths more difficult.
Thin films of amorphous and polycrystalline silicon are widely used in semiconductor manufacturing. For example, amorphous silicon can be used for the formation at the gate of CMOS structures for application in the dual gate process since the amorphous silicon can effectively reduce the Boron (B) penetration from the gate to the device region. Doped polycrystalline silicon can be used to form interconnects, gate electrodes, emitter structures and resistors. These silicon thin films are typically formed by LPCVD (low pressure chemical vapor deposition) by decomposition of a silicon containing gas such as silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6). Doping can also be accomplished in the gas phase by introducing a dopant gas such as diborane (B.sub.2 H.sub.6), arsine (AsH.sub.3) or phosphine (PH.sub.3). The deposition temperature during LPCVD is typically from 500 degrees C. to 675 degrees C. and the pressure is typically from 200 mTorr to 2 Torr. The crystalline structure of the `as deposited` film is largely a function of the deposition temperature. At temperatures below about 550 degrees C. the `as deposited` films have an amorphous structure. At temperatures between about 550 degrees C. and 580 degrees C., there is a transition between amorphous silicon and polycrystalline silicon. Hemispherical grain (HSG) polysilicon is typically grown in this transitional range. At temperatures above about 580 degrees C. the `as deposited` films have a polycrystalline structure.
In addition to LPCVD, there are other methods for depositing thin films of amorphous and polycrystalline silicon. One such method is plasma-enhanced chemical vapor deposition (PECVD) and rf induced glow discharge is used to transfer energy into the reactant gases. Advantages of PECVD include lower substrate temperatures and higher deposition rates. A representative temperature range for PECVD of silicon thin films is about 350 degrees C. to 450 degrees C. Another method of depositing amorphous and polycrystalline silicon thin films is RTCVD (rapid thermal chemical vapor deposition). With RTCVD the structure is typically rapidly heated by lamps and the reactant gases are introduced.
One problem that occurs during deposition of in-situ doped amorphous or polycrystalline silicon thin film is the degradation of the underlying substrate film by reacting of the dopant species with contaminants on the substrate. Specifically, an underlying substrate can be attacked by acidic gasses formed by the dopant species during the deposition process. For example, with a phosphine (PH.sub.3) dopant, phosphoric acid (H.sub.3 PO.sub.4) can be generated by the reaction of phosphine (PH.sub.3) with oxygen (O.sub.2) or water (HO.sub.2) present in the substrate or in the reactor chamber. Phosphoric acid is highly corrosive and can attack an underlying film such as silicon nitride (Si.sub.3 N.sub.4).
These problems are compounded by the increased use of HSG or rugged polysilicon. This type of polysilicon increases the surface area and the `trapping` area on the substrate for contaminants. In addition, during CVD of silicon, the deposition process does not occur immediately upon introduction of the reactant gasses. This gives the reactant gasses time to combine with corrosive by-products, which can attack the unprotected substrate.
The lower part (the conductive part) of a gate electrode typically is either polysilicon or amorphous silicon or a combination of both. This layer may be in-situ doped with dopant atoms or ion implanted with dopant atoms to alter the conductivity pattern of this conductive layer.
Amorphous silicon will transition into polycrystalline silicon by increasing the temperature, for instance above 550 degrees C. At this temperature, hemispherical grain (HSG) polysilicon is typically grown in this transition range. It is from the above clear that a method for the accurate evaluation of the HSG film is required.
Dynamic Random Memory (DRAM) technology has seen dramatic improvements in memory capacity driven by equally dramatic reduction in device feature sizes from 0.8 um (4M DRAM) to 0.25 um (256M DRAM). The basic unit of a DRAM cell contains one transistor and one storage capacitor. The DRAM storage capacitor can be of trench construction or a stacked capacitor type. In the construction of DRAM cells, the deposition of polysilicon layers is a significant part of this construction, for instance a layer of HSG can form the bottom electrode of the DRAM capacitor. The invention concentrates on measuring the reflectivity of an as-deposited layer of HSG on the surface of a blank wafer. The layer of HSG forms one of the layers in the construction of the capacitive unit of a DRAM cell; the quality of the deposited layer of HSG is an important factor in controlling the DRAM fabrication process. The HSG film quality can be measured by measuring the surface reflectivity of the layer of HSG. It is thereby of particular interest to derive the device ultimate capacitance value from the quality of the deposited layer of HSG. This makes it important that a correlation between this ultimate capacitance value and the Reflectivity Index (RI) of the deposited layer of HSG can be established.
FIG. 1 shows the Prior Art method of determining the surface quality of a deposited layer of HSG. A layer 12 of HSG has been deposited on the surface of a bare wafer 10. The surface shows surface irregularities 14, 16 and 18 where 14 can be described as the width of the surface roughness at the widest lower part of the surface roughness, 16 as the width of the surface roughness at the narrowest upper part of the surface roughness and 18 as the depth of the surface roughness. All of these parameters by their very nature, a indeterminate in value and can, for a theoretical analysis, only be approached by means of their statistical mean or average values. Suffice it to say at this point that a high value of 18 indicates a rough surface whereby the relative values of 14 compared with 16 gives an indication of the type of roughness of the surface. For instance a small value for the ratio 14/16 indicates that the openings at the top of the surface roughness features are large compared with the bottom areas of the roughness, the surface roughness in this case can resemble a structure of adjacent equilateral rectangles with the hypotenuse of these rectangles being in the plane of the substrate. The inverse consideration leads to a surface roughness that resembles a sequence of inverted equilateral rectangles with the hypotenuse of these rectangles being parallel to but at a distance of the plane of the substrate. The actual surface roughness can also be a combination of these two phenomenon where either one aspect or the other might dominate or might not dominate but be equally present. The key aspect is that, independent of the profile of the actual cross section of the surface roughness, a significant number of openings 20 exist between and within the deposited layer 12 of HSG.
The Prior Art method of determining HSG layer surface quality uses a Scanning Electron Microscope (SEM) analysis of this surface. This method of surface analysis is limited since it cannot detect the quantitative nature of the cross section of area 14. This area is hidden from view for the SEM and can therefore not be analyzed. It is also possible that opening 16 is narrow enough that the presence of area 14 is overlooked during the SEM based analysis.
Another Prior Art technique to evaluate the quality of the HSG surface is the measure the Reflectivity Index (RI) of the surface. This RI at best is representative of the macro-roughness of the HSG surface but overlooks, dependent on the relative dimensions of 12, 14, 16 and 18, micro aspects of the surface quality. The RI also does not correlate with the ultimate capacitance value where the HSG layer is used as the bottom plate of a DRAM capacitor.
HSG surface smoothness can be evaluated by establishing and measuring a parameter that is representative of the volume of these openings 20. The larger this volume, the rougher the surface of the deposited layer of HSG. The lower this volume, the smoother the surface of the deposited layer of HSG which, when using a layer of HSG in the construction of a semiconductor device, is the preferred HSG layer surface characteristic.
U.S. Pat. No. 5,604,157 (Dai et al.) and U.S. Pat. No. 5,554,566 (Lur et al.) show HSG process.